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datasheet 9dbl0841 / 9dbl0851 february 9, 2017 1 ?2017 integrated device technology, inc. 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 description the 9dbl0841 / 9dbl0851 devices are 3.3v members of idt's full-featured pcie fa mily. the 9dbl0841 / 9dbl0851 supports pcie gen1-4 common clocked (cc) and pcie separate reference independent spread (sris) systems. it offers a choice of integrated output terminations providing direct connection to 85 ? or 100 ? transmission lines. the 9dbl08p1 can be factory programmed with a user-defined power up default smbus configuration. recommended application pcie gen1-4 clock distribution for riser cards, storage, networking, jbod, communications, access points output features ? 8 ? 1-200 mhz low-power (lp) hcsl dif pairs ? 9dbl0841 default z out = 100 ? ? 9dbl0851 default z out = 85 ? ? 9dbl08p1 factory programmable defaults ? easy ac-coupling to other logic families, see idt application note an-891 key specifications ? pcie gen1-2-3-4 cc co mpliant in zdb mode ? pcie gen2 sris compliant in zdb mode ? supports pcie gen2-3 sris in fan-out mode ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew < 50ps ? bypass mode additive phase jitter is 0 ps typical rms for pcie ? bypass mode additive phase jitter 160fs rms typ. @ 156.25m (1.5m to 10m) features/benefits ? direct connection to 100 ? (0841) or 85 ? (0851) transmission lines; saves 32 resistors compared to standard pcie devices ? 211mw typical power consumption (pll mode@3.3v); eliminates thermal concerns ? vddio allows 35% power savings at optional 1.05v; maximum power savings ? smbus-selectable features allows optimization to customer requirements: ? control input polarity ? control input pull up/downs ? slew rate for each output ? differential output amplitude ? output impedance for each output ? 50, 100, 125mhz operating frequency ? customer defined smbus power up default can be programmed into p1 device; allows exact optimization to customer requirements ? oe# pins; support dif power management ? hcsl-compatible differential input; can be driven by common clock sources ? spread spectrum tolerant; allows reduction of emi ? pin/smbus selectable pll bandwidth and pll bypass; minimize phase jitter for each application ? outputs blocked until pll is locked; clean system start-up ? device contains default confi guration; smbus interface not required for device operation ? three selectable smbus addres ses; multiple devices can easily share an smbus segment ? space saving 48-pin 6x6mm vfqfpn; minimal board space block diagram note: resistors default to internal on 41/51 devices. p1 devices ha ve programmable default impedances on an output-by-output basis. xin/clkin_25 x2 control logic vss_en_tri ^ckpwrgd_pd# sdata_3.3 ss capable pll osc ref3.3 voe(7:0)# sclk_3.3 vsadr dif0 dif1 dif2 dif3 dif4 dif5 dif6 dif7
8-output 3.3v pcie zero-d elay buffer 2 february 9, 2017 9dbl0841 / 9dbl0851 datasheet pin configuration smbus address selection table power management table power connections pll operating mode ^ckpwrgd_pd# vddio voe7# dif7# dif7 voe6# dif6# dif6 gnd vddio vdd3.3 voe5# 48 47 46 45 44 43 42 41 40 39 38 37 vsadr_tri 1 36 dif5# ^vhibw_bypm_lobw# 2 35 dif5 fb_dnc 3 34 voe4# fb_dnc# 4 33 dif4# vddr3.3 5 32 dif4 clk_in 6 31 vddio clk_in# 7 30 vdda3.3 gndr 8 29 gnda gnddig 9 28 voe3# sclk_3.3 10 27 dif3# sdata_3.3 11 26 dif3 vdddig3.3 12 25 voe2# 13 14 15 16 17 18 19 20 21 22 23 24 vddio voe0# dif0 dif0# voe1# dif1 dif1# vdd3.3 vddio gnd dif2 dif2# ^v prefix indicates internal 120kohm pull up and pull down resistor (biased to vdd/2) v prefix indicates internal 120kohm pull down resistor ^ prefix indicates internal 120kohm pull up resistor 9dbl0841/51/p1 epad is gnd 48-pin vfqfpn, 6x6 mm, 0.4mm pitch sadr address 0 1101011 m 1101100 1 1101101 x x state of sadr on first application of ckpwrgd_pd# + read/write bit x note: if not using ckpwrgd (ckpwrgd tied to vdd3.3), all 3.3v vdd need to transition from 2.1v to 3.135v in <300usec. true o/p comp. o/p 0xxx low 1 low 1 off 1 running 0 x low 1 low 1 on 2 1 running 1 0 running running on 2 1 running 1 1 low 1 low 1 on 2 1. the output state is set by b11[1:0] (low/low default) pll difx ckpwrgd_pd# smbus oex bit 2. if bypass mode is selected, the pll will be off, and outputs will be running. clk_in oex# pin pin number vdd vddio gnd 58 input receiver analog 12 9 di g ital power 20,31,38 13,21,31, 39,47 22, 29,40,49 dif outputs 30 29 pll analog description hibw_bypm_lobw# mode byte1 [7:6] readback byte1 [4:3] control 0 pll lo bw 00 00 m bypass 01 01 1 pll hi bw 11 11
february 9, 2017 3 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet pin descriptions pin # pin name type description 1 vsadr_tri latched in tri-level latch to select smbus address. see smbus address selection table. 2 ^ vhibw_bypm_lobw # latched in trilevel input to select high bw, bypass or low bw mode. this pin is biased to vdd/2 (bypass mode) with internal pull up/pull down resistors. see pll operating mode table for details. 3 fb_dnc dnc true clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 4 fb_dnc# dnc complement clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 5 vddr3.3 pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differential reference clock. 7 clk_in# in complementary input for differential reference clock. 8 gndr gnd analog ground pin for the differential input (receiver) 9 gnddig gnd gr ound pin for digital circuitry 10 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 11 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 12 vdddig3.3 pwr 3.3v digital power (dirty power) 13 vddio pwr power supply for differential outputs 14 voe0# in active low input for enabling output 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 15 dif0 out differential true clock output 16 dif0# out differential complementary clock output 17 voe1# in active low input for enabling output 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 vdd3.3 pwr power supply, nominal 3.3v 21 vddio pwr power supply for differential outputs 22 gnd gnd ground pin. 23 dif2 out differential true clock output 24 dif2# out differential complementary clock output 25 voe2# in active low input for enabling output 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 26 dif3 out differential true clock output 27 dif3# out differential complementary clock output 28 voe3# in active low input for enabling output 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 29 gnda gnd ground pin for the pll core. 30 vdda3.3 pwr 3.3v power for the pll core. 31 vddio pwr power supply for differential outputs 32 dif4 out differential true clock output 33 dif4# out differential complementary clock output 34 voe4# in active low input for enabling output 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 35 dif5 out differential true clock output 36 dif5# out differential complementary clock output 37 voe5# in active low input for enabling output 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 38 vdd3.3 pwr power supply, nominal 3.3v 39 vddio pwr power supply for differential outputs
8-output 3.3v pcie zero-d elay buffer 4 february 9, 2017 9dbl0841 / 9dbl0851 datasheet pin descriptions (cont.) test loads alternate terminations the 9dbl family can easily drive lvpecl, lvds, and cml logic. see ?an-891 driving lvpecl, lvds, and cml logic with idt's "universal" low-power hcsl outputs? for details. pin # pin name type description 40 gnd gnd ground pin. 41 dif6 out differential true clock output 42 dif6# out differential complementary clock output 43 voe6# in active low input for enabling output 6. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 44 dif7 out differential true clock output 45 dif7# out differential complementary clock output 46 voe7# in active low input for enabling output 7. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 47 vddio pwr power supply for differential outputs 48 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 49 epad gnd connect to ground. 2pf l inches differential zo 2pf low-power push-pull hcsl output test load (integrated terminations) terminations device zo ( ? )rs ( ? ) 9dbl0841 100 none needed 9dbl0851 100 7.5 9dbl08p1 100 prog. 9dbl0841 85 n/a 9dbl0851 85 none needed 9dbl08p1 85 prog.
february 9, 2017 5 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet absolute maximum ratings stresses above the ratings listed below ca n cause permanent damage to the 9dbl08 41 / 9dbl0851. these ratings, which are standard values for idt commercially rated part s, are stress ratings only. functional o peration of the device at these or any o ther conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteris tics?smbus parameters electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes supply voltage vddx 4.6 v 1,2 input voltage v in -0.5 v dd +0.5 v 1,3 input high voltage, smbus v ihsmb smbus clock and data pins 3.9 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2500 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 4.6v. ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes smbus input low voltage v ilsmb v ddsmb = 3.3v 0.8 v smbus input high voltage v ihsmb v ddsmb = 3.3v 2.1 3.6 v smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 2.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f smb smbus operating frequency 500 khz 2,3 1 guaranteed by design and characterization, not 100% tested in production. 2. the device must be powered up for the smbus to function. 3. the differential input clock must be running for the smbus to be active ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input crossover voltage - dif_in v cross cross over voltage 150 900 mv 1 input swing - dif_in v swing differential value 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
8-output 3.3v pcie zero-d elay buffer 6 february 9, 2017 9dbl0841 / 9dbl0851 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddx supply voltage for core and analog 3.135 3.3 3.465 v output supply voltage vddio supply voltage for low power hcsl outputs 0.95 1.05-3.3 3.465 v ambient operating temperature t amb industrial range -40 25 85 c input high voltage v ih 0.75 v ddx v ddx + 0.3 v input low voltage v il -0.3 0.25 v ddx v input high voltage v ihtri 0.75 v ddx v dd + 0.3 v input mid voltage v imtri 0.4 v ddx 0.5 v ddx 0.6 v ddx v input low voltage v iltri -0.3 0.25 v ddx v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -50 50 ua bypass mode 1 200 mhz 2 100mhz pll mode 60 100.00 140 mhz 2 50mhz pll mode 30 50.00 65 mhz 2 125mhz pll mode 75 125.00 175 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1 c ou t output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency pcie f modi npci e allowable frequency for pcie applications (triangular modulation) 30 33 khz input ss modulation frequency non-pcie f modi n allowable frequency for non-pcie applications (triangular modulation) 066khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. input current single-ended inputs, except smbus single-ended tri-level inputs ('_tri' suffix) 3 time from deassertion until outputs are >200 mv input frequency f in capacitance
february 9, 2017 7 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet electrical characteristics? dif low-power hcsl outputs electrical characteristi cs?current consumption ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes dv/dt scope avera g in g on, fast settin g 22.84 v/ns 1,2,3 dv/dt scope avera g in g on, slow settin g 1.2 1.9 3.1 v/ns 1,2,3 slew rate matching dv/dt slew rate matching 7 20 % 1,2,4 voltage high v hi gh 660 768 850 7 voltage low v low -150 -11 150 7 max voltage vmax 811 1150 7 min voltage vmin -300 -49 7 crossing voltage (abs) vcross_abs scope averaging off 250 357 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 14 140 mv 1,6 2 measured from differential waveform 7 at default smbus settings. slew rate statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by desi g n and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i dda vdda, pll mode, @100mhz 7 10 ma i dd vddx, all outputs active @100mhz 22 32 ma i ddi o vddio, all outputs active @100mhz 35 45 ma i ddapd vdda, ckpwrgd_pd#=0 0.6 1 ma 2 i ddpd vddx, ckpwrgd_pd#=0 4.9 7 ma 2 i ddi opd vddio, ckpwrgd_pd#=0 0.04 0.10 ma 2 1 guaranteed by design and characterization, not 100% tested in production. 2 input clock stopped. powerdown current operating supply current
8-output 3.3v pcie zero-d elay buffer 8 february 9, 2017 9dbl0841 / 9dbl0851 datasheet electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics electrical characteristics?fi ltered phase jitter parameters - pc ie common clocked (cc) architectures ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes -3db point in high bw mode (100mhz) 2 3.3 4 mhz 1,5 -3db point in low bw mode (100mhz) 1 1.5 2 mhz 1,5 pll jitter peaking t jpeak peak pass band gain (100mhz) 0.8 2 db 1 duty cycle t d c measured differentially, pll mode 45 50 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode -1 0.0 1 % 1,3 t p dbyp bypass mode, v t = 50% 2500 3406 4500 ps 1 t p dpll pll mode v t = 50% -100 8 100 ps 1,4 skew, output to output t sk3 v t = 50% 21 55 ps 1,4 pll mode 15 50 ps 1,2 additive jitter in bypass mode 0.1 1 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform 3 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 4 all outputs at default slew rate 5 the min/typ/max values of each bw setting track each other, i.e., low bw max will never occur with hi bw min. pll bandwidth bw skew, input to output jitter, cycle to cycle t jcyc-cyc t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jp hpcieg1-c c pcie gen 1 23 32 86 ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 0.6 0.8 3 ps (rms) 1,2,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 1.7 2.1 3.1 ps (rms) 1,2,5 t jphpcieg3-cc pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.4 0.48 1 ps (rms) 1,2,5 t jphpcieg4-cc pcie gen 4 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.4 0.48 0.5 ps (rms) 1,2,5 t jphpcieg1-cc pcie gen 1 0.0 0.01 ps (p-p) 1,2,5 pcie gen 2 lo band 10khz < f < 1.5mhz (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 0.0 0.01 ps (rms) 1,2,4,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 0.0 0.01 ps (rms) 1,2,4,5 t jphpcieg3-cc pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.0 0.01 ps (rms) 1,2,4,5 t jphpcieg4-cc pcie gen 4 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.0 0.01 ps (rms) 1,2,4,5 1 applies to all outputs. 5 driven by 9fgl0841 or equivalent phase jitter, pll mode t jphpcieg2-cc additive phase jitter, bypass mode n/a t jphpcieg2-cc 2 based on pcie base specification rev4.0 version 0.7draft. see http://www.pcisig.com for latest specifications. 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 for rms values additive jitter is calculated by solvin g the followin g equation for b [ a^2+b^2=c^ 2 ] where a is rms input jitter and c is rms total jitter.
february 9, 2017 9 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet electrical characteristics?filtered pha se jitter parameters - pcie separate reference independent spr ead (sris) architectures 5 electrical characteristics?unfilt ered phase jitter parameters t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jphpcieg2-sris pcie gen 2 (pll bw of 16mhz , cdr = 5mhz) 1.2 1.5 2 ps (rms) 1,2 t jphpcieg3-sris pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.5 ps (rms) 1,2,6 t jphpcieg2-sris pcie gen 2 (pll bw of 16mhz , cdr = 5mhz) 0.0 0.01 ps (rms) 1,2,4 t jphpcieg3-sris pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.0 0.01 ps (rms) 1,2,4,6 1 applies to all outputs. phase jitter, pll mode n/a 6 this device does not support pcie gen3 sris in pll mode. it supports pcie gen3 sris in bypass mode. additive phase jitter, bypass mode n/a 2 based on pcie base specification rev3.1a. these filters are different than common clock filters. see http://www.pcisig.com for latest specifications. 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 for rms values, additive jitter is calculated by solving the following equation for b [ a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter. 5 as of pcie base specification rev4.0 draft 0.7, sris is not currently defined for gen1 or gen4. ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jph156m 156.25mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 159 n/a fs (rms) 1,2,3 t jph156m12k-20 156.25mhz, 12khz to 20mhz, -20db/decade rollover <12khz, -40db/decade rolloff > 20mhz 363 n/a fs (rms) 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. 3 for rms figures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total jitter)^2 - (i nput jitter)^2] additive phase jitter, fanout mode 2 driven by rohde&schartz sma100
8-output 3.3v pcie zero-delay buffer 10 february 9, 2017 9dbl0841 / 9dbl0851 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is latched on sadr pin. unless otherwise indicated, default values are for the 0841 and 0851. p1 devices are fully factory programmable. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
february 9, 2017 11 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe7 output enable rw pin control 1 bit 6 dif oe6 output enable rw pin control 1 bit 5 dif oe5 output enable rw pin control 1 bit 4 dif oe4 output enable rw pin control 1 bit 3 dif oe3 output enable rw pin control 1 bit 2 dif oe2 output enable rw pin control 1 bit 1 dif oe1 output enable rw pin control 1 bit 0 dif oe0 output enable rw pin control 1 1. a low on these bits will overide the oe# pin and force the differential output to the state indicated by b11[1:0] (low/low d efault) smbus table: pll operating mode and output amplitude control register byte 1 name control function type 0 1 default bit 7 pllmoderb1 pll mode readback bit 1 r latch bit 6 pllmoderb0 pll mode readback bit 0 r latch bit 5 pllmode_swcntrl enable sw control of pll mode rw values in b1[7:6] set pll mode values in b1[4:3] set pll mode 0 bit 4 pllmode1 pll mode control bit 1 rw 1 0 bit 3 pllmode0 pll mode control bit 0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01= 0.68v 1 bit 0 amplitude 0 rw 10 = 0.75v 11 = 0.85v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 slewratesel dif7 adjust slew rate of dif7 rw slow setting fast setting 1 bit 6 slewratesel dif6 adjust slew rate of dif6 rw slow setting fast setting 1 bit 5 slewratesel dif5 adjust slew rate of dif5 rw slow setting fast setting 1 bit 4 slewratesel dif4 adjust slew rate of dif4 rw slow setting fast setting 1 bit 3 slewratesel dif3 adjust slew rate of dif3 rw slow setting fast setting 1 bit 2 slewratesel dif2 adjust slew rate of dif2 rw slow setting fast setting 1 bit 1 slewratesel dif1 adjust slew rate of dif1 rw slow setting fast setting 1 bit 0 slewratesel dif0 adjust slew rate of dif0 rw slow setting fast setting 1 note: see "low-power hcsl outputs" table for slew rates. smbus table: frequency select control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 freq_sel_en enable sw selection of frequency rw sw frequency change disabled sw frequency change enabled 0 bit 4 fsel1 freq. select bit 1 rw 1 0 bit 3 fsel0 freq. select bit 0 rw 1 0 bit 2 1 bit 1 1 bit 0 slewratesel fb adjust slew rate of fb rw slow setting fast setting 1 1. b3[5] must be set to a 1 for these bits to have any effect on the part. byte 4 is reserved see b11[1:0] reserved reserved see pll operating mode table see pll operating mode table reserved controls output amplitude reserved reserved 00 = 100m, 10 = 125m 01 = 50m, 11= reserved
8-output 3.3v pcie zero-delay buffer 12 february 9, 2017 9dbl0841 / 9dbl0851 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 1 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 rw 0 bit 6 device type0 rw 1 bit 5 device id5 rw 0 bit 4 device id4 rw 0 bit 3 device id3 rw 1 bit 2 device id2 rw 0 bit 1 device id1 rw 0 bit 0 device id0 rw 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 bytes 8 and 9 are reserved smbus table: pd_restore byte 10 name control function type 0 1 default bit 7 1 bit 6 power-down (pd) restore restore default config. in pd rw clear config in pd keep config in pd 1 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved byte count programming vendor id device id reserved revision id 0001 = idt reserved reserved device type writing to this register will configure how many bytes will be read back, default is = 8 bytes. reserved reserved reserved reserved 001000 binary or 08 hex 00 = fgx, 01 = dbx zdb/fob, 10 = dmx, 11= dbx fob b rev = 0001 reserved
february 9, 2017 13 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet smbus table: impedance control byte 11 name control function type 0 1 default bit 7 fb_imp[1] rw 00=33 dif zout 10=100 dif zout bit 6 fb_imp[0] rw 01=85 dif zout 11 = reserved bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 stp[1] rw 00 = low/low 10 = high/low 0 bit 0 stp[0] rw 01 = hiz/hiz 11 = low/high 0 note: xx41 = 10, xx51 = 01, p1 = factory programmable. smbus table: impedance control byte 12 name control function type 0 1 default bit 7 dif3_imp[1] dif3 zout rw 00=33 dif zout 10=100 dif zout bit 6 dif3_imp[0] dif3 zout rw 01=85 dif zout 11 = reserved bit 5 dif2_imp[1] dif2 zout rw 00=33 dif zout 10=100 dif zout bit 4 dif2_imp[0] dif2 zout rw 01=85 dif zout 11 = reserved bit 3 dif1_imp[1] dif1 zout rw 00=33 dif zout 10=100 dif zout bit 2 dif1_imp[0] dif1 zout rw 01=85 dif zout 11 = reserved bit 1 dif0_imp[1] dif0 zout rw 00=33 dif zout 10=100 dif zout bit 0 dif0_imp[0] dif0 zout rw 01=85 dif zout 11 = reserved note: xx41 = 10, xx51 = 01, p1 = factory programmable. smbus table: impedance control byte 13 name control function type 0 1 default bit 7 dif7_imp[1] dif7 zout rw 00=33 dif zout 10=100 dif zout bit 6 dif7_imp[0] dif7 zout rw 01=85 dif zout 11 = reserved bit 5 dif6_imp[1] dif6 zout rw 00=33 dif zout 10=100 dif zout bit 4 dif6_imp[0] dif6 zout rw 01=85 dif zout 11 = reserved bit 3 dif5_imp[1] dif5 zout rw 00=33 dif zout 10=100 dif zout bit 2 dif5_imp[0] dif5 zout rw 01=85 dif zout 11 = reserved bit 1 dif4_imp[1] dif4 zout rw 00=33 dif zout 10=100 dif zout bit 0 dif4_imp[0] dif4 zout rw 01=85 dif zout 11 = reserved note: xx41 = 10, xx51 = 01, p1 = factory programmable. smbus table: pull-up pull-down control byte 14 name control function type 0 1 default bit 7 oe3_pu/pd[1] rw 00=none 10=pup 0 bit 6 oe3_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 5 oe2_pu/pd[1] rw 00=none 10=pup 0 bit 4 oe2_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 3 oe1_pu/pd[1] rw 00=none 10=pup 0 bit 2 oe1_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 1 oe0_pu/pd[1] rw 00=none 10=pup 0 bit 0 oe0_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 note: these values are for xx41 and xx51. p1 is factory programmable. feedback zout reserved reserved reserved reserved true/complement dif output disable state see note see note oe3 pull-up(pup)/ pull-down(pdwn) control oe2 pull-up(pup)/ pull-down(pdwn) control oe1 pull-up(pup)/ pull-down(pdwn) control oe0 pull-up(pup)/ pull-down(pdwn) control see note
8-output 3.3v pcie zero-delay buffer 14 february 9, 2017 9dbl0841 / 9dbl0851 datasheet byte 15 name control function type 0 1 default bit 7 oe7_pu/pd[1] rw 00=none 10=pup 0 bit 6 oe7_pu/pd0] rw 01=pdwn 11 = pup+pdwn 1 bit 5 oe6_pu/pd[1] rw 00=none 10=pup 0 bit 4 oe6_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 3 oe5_pu/pd[1] rw 00=none 10=pup 0 bit 2 oe5_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 1 oe4_pu/pd[1] rw 00=none 10=pup 0 bit 0 oe4_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 note: these values are for xx41 and xx51. p1 is factory programmable. smbus table: pull-up pull-down control byte 16 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 ckpwrgd_pd_pu/pd[1] rw 00=none 10=pup 1 bit 0 ckpwrgd_pd_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 0 note: these values are for xx41 and xx51. p1 is factory programmable. bytes 17 is reserved and and reads back 0h00. smbus table: polarity control byte 18 name control function type 0 1 default bit 7 oe7_polarity sets oe7 polarity rw enabled when low enabled when high 0 bit 6 oe6_polarity sets oe6 polarity rw enabled when low enabled when high 0 bit 5 oe5_polarity sets oe5 polarity rw enabled when low enabled when high 0 bit 4 oe4_polarity sets oe4 polarity rw enabled when low enabled when high 0 bit 3 oe3_polarity sets oe3 polarity rw enabled when low enabled when high 0 bit 2 oe2_polarity sets oe2 polarity rw enabled when low enabled when high 0 bit 1 oe1_polarity sets oe1 polarity rw enabled when low enabled when high 0 bit 0 oe0_polarity sets oe0 polarity rw enabled when low enabled when high 0 smbus table: polarity control byte 19 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 ckpwrgd_pd determines ckpwrgd_pd polarity rw power down when low power down when high 0 reserved reserved reserved reserved reserved oe6 pull-up(pup)/ pull-down(pdwn) control oe5 pull-up(pup)/ pull-down(pdwn) control oe4 pull-up(pup)/ pull-down(pdwn) control reserved reserved reserved reserved reserved reserved reserved reserved ckpwrgd_pd pull-up(pup)/ pull-down(pdwn) control oe7 pull-up(pup)/ pull-down(pdwn) control
february 9, 2017 15 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes country of origin. 3. yyww is the last two digits of the year and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. thermal characteristics ics dbl0841bi yyww coo lot ics dbl0851bi yyww coo lot ics b8p1000i yyww coo lot parameter symbol conditions pkg typ value units notes jc junction to case 33 c/w 1 c/w 1 junction to air, still air 37 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 26 c/w 1 1 epad soldered to board thermal resistance ndg48
8-output 3.3v pcie zero-delay buffer 16 february 9, 2017 9dbl0841 / 9dbl0851 datasheet package outline and dimensions (ndg48)
february 9, 2017 17 8-output 3.3v pcie zero-delay buffer 9dbl0841 / 9dbl0851 datasheet package outline and dimensions (ndg48), cont.
8-output 3.3v pcie zero-delay buffer 18 february 9, 2017 9dbl0841 / 9dbl0851 datasheet ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?b? is the device revision designator (wil l not correlate with the datasheet revision). ?xxx? is a unique factory assigned number to identify a particular default configuration. revision history part / order number notes shipping packaging package temperature 9dbl0841bkilf trays 48-pin vfqfpn -40 to +85 c 9dbl0841bkilft tape and reel 48-pin vfqfpn -40 to +85 c 9dbl0851bkilf trays 48-pin vfqfpn -40 to +85 c 9dbl0851bkilft tape and reel 48-pin vfqfpn -40 to +85 c 9DBL08P1BXXXKILF trays 48-pin vfqfpn -40 to +85 c 9DBL08P1BXXXKILFt tape and reel 48-pin vfqfpn -40 to +85 c 100 ? 85 ? factory configurable. contact idt for addtional information. rev. initiator issue date description page # a rdw 5/312016 1. add pcie g1-4 common clock and pcie sris to electrical tables 2. update electrical tables to final 3. changed '1' value in byte 0 to indicate "pin control" 4. stylistic update to block diagram 5. minor updates to smbus registers 0 and 1 for readab ility 6. front page text update for family consistency. 7. removed '000' code from ordering information, updated table. 8. updated smbus byte 1[1:0] description 9. update smbus byte 11[1:0] description various b rdw 6/14/2016 1. electrical table and smbus updates/corrections 2. smbus operating frequency is now set to 500khz max. 3. removed duplicate absolute maximum table. 4. release to final. various c rdw 6/21/2016 1.max smbus freq changed from 400khz to 500khz. 2. page 13. byte 11[7:6] are now renamed.. 3. page 14. byte 16 - bits 3 and 2 are now reserved. references to 9dbl09xx devices in footnote removed. 4. page 14. byte 19 - bit 1 is reserved 5,13,14 d rdw 8/8/2016 1. minor corrections to footnotes on electrical tables various e rdw 2/9/2017 updated datasheet part numbering to be 9dbl0841/9dbl0851. various
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